(1) Field of the Invention
The present invention relates to an improved vertical type MOS transistor for preventing destruction of the transistor element or elements, and its chip from a surge voltage of current.
(2) Description of the Prior Art
The vertical type MOS transistor is useful as a power switching element and it has many applications. One example of the vertical type MOS transistor is described in a monthly magazine "ELECTRONICS", June volume, p. 587, 1982 issued by Ohm Publishing Co., Ltd.
FIG. 4 shows a cross-sectional view of the vertical type N-channel MOS transistor of the type according to the prior art. The vertical type MOS transistor consists of a N.sup.+ - type substrate 1, a N-type drain region 3 formed thereon, a plurality of P-type well regions 9 formed by impurity diffusion in the N-type drain region 3, with a predetermined distance spaced apart, and N.sup.+ -type source regions 11 and a P.sup.+ type well contact region 13 sandwiched between the N.sup.+ - type source regions, all of the substrate 1 and the different regions being electrically conductive and the N.sup.+ - type source regions 11 and the P.sup.+ -type well contact region 13 being formed by impurity diffusion in each P-type well region 9 respectively.
The extension region 3a of the N-type drain region, which continuously extends from the region 3, is formed between the P-type well regions 9 and an electrode as a gate electrode 17 is formed on the surfaces of the part 3a of the N-type region 3 and each part of the P-type regions 9, through a gate oxide film 15. On the other side of the N.sup.+ -type substrate 1, there is provided another electrode 7 as a drain electrode.
In addition, on the gate electrode 17, there is provided a source electrode 19 through an insulated layer 21. The N.sup.+ -type substrate 1, N-type drain region 3, and P-type regions 9, etc., constitute a semiconductor layer 5. With this construction, when a voltage is applied to the gate electrode 17, a conduction channel is formed on the surface of the P-type well regions 9 just below the gate oxide film 15, and current between the source and drain is controlled through this conduction channel.
In the vertical type MOS transistor according to the prior art, however, as it is used as a power MOS transistor, when a relatively high voltage is applied between the source and the drain, a breakdown begins to occur at the corner of the P-N junction indicated by an arrow 10 between the N-type drain region 3 and the Ptype well region 9 because the concentration of the electric field occurs at the corner, and then the current caused by the breakdown causes a parasitic bipolar transistor formed in parallel with the MOS transistor to be turned on. The operation of the bipolar transistor in turn causes the concentration of the current in the area between the N-type drain region 3 and the P-type well region 9 and the MOS transistor often is destroyed by the heat caused by the current.
This problem is liable to occur when a surge voltage larger than a predetermined voltage tolerance or durability of the MOS transistor is applied between the source and the drain.